18 comments

  • loloquwowndueo 1 hour ago
    So this was all just simulated? Where are the pictures of the build?

    Back in the day i built a 4-bit CPU on a breadboard (it was huge actually spanned 3 breadboards). Programming the ROM by hand like cavemen (to be fair it was the cave ages). We didn’t carry cameras in our pockets so sadly we didn’t get a picture.

    • intrasight 33 minutes ago
      My "back in the day" project, which everyone in class (could work in team up to 3) had to do was a wirewrapped breadboarded 8-bit CPU. We had to demonstrate it solving some problem. Extra points for doing something with an I/O channel.

      At the end, my team drew straws to see who would get to keep it. Alas, I didn't win.

      CMU in 1986.

  • pjc50 3 hours ago
    This is also very well documented. Probably as part of the assessment, but it's nice to see.

    It doesn't appear to have any kind of interrupts, which is quite a limitation for actual usecases, but also makes the architecture much simpler.

    The use of dual phase clocking is interesting. The document describes it as having the control and data paths operating on opposite phases. I'm curious as to where you got this technique from, since it's not common (apart from the use of both edges by DDR RAM). I also suspect that it would go away if you had better tooling for managing setup and hold violations (does logisim do that for you, or did you have to manage it manually somehow?). Not all FPGA tools like nonstandard clock architectures.

    • sehugg 2 hours ago
      The dual phase clocking is perhaps inspired by the 6502.
  • gabrielsroka 11 hours ago
    Ben Eater's SAP came from "Digital Computer Electronics" by Albert Paul Malvino and Jerald A. Brown

    https://en.wikipedia.org/wiki/Simple-As-Possible_computer

    • dyauspitr 9 hours ago
      Yep this is how I built my SAP 20 years ago.
  • gsliepen 4 hours ago
    Very nice. I wonder if implementing a one-instruction set computer (for example something that implements Adrian Cable's subleq VM, see https://www.ioccc.org/2025/cable/) would be educational and whether it can make the design of a computer from discrete logic chips simpler or more complex. Though it would very likely not be as efficient.
  • osigurdson 9 hours ago
    A 2nd year project back in the day was to build a 4 bit CPU on a breadboard. We had the advantage of having an ALU IC but was still quite tough to get working!
    • tralarpa 2 hours ago
      You were in good company. The Xerox Alto CPU used four 74181 ALUs.
  • peterus 11 hours ago
    Awesome project, re fpga implementation one option you might want to explore are used Bitcoin miner control boards if you want the best logic units/$ ratio. I've used the EBAZ4205 (zynq 7010) control boards with a cheap/generic FT2232HL dev board and it works great. Of course it's a bit more of a pain compared to a regular dev board
    • wildzzz 10 hours ago
      If they are taking digital design classes, they'll probably be given something like a DE0-Nano that can run this just fine.
  • jdw64 9 hours ago
    I did something similar for a school capstone project. It brings back memories. Writing Verilog, working with FPGAs, that sort of thing. But this goes even further and actually gets into hardwired implementation, which is really impressive. Actually, using if else statements just creates MUXes, so you don't have fanout issues to worry about. But for something like this, you would have to handle timing calculations for rising and falling edges. It is really remarkable.
  • assimpleaspossi 1 hour ago
    >>me and my friends ...

    My friends and I...

    • jen729w 6 minutes ago
      If you're going to be a pointless language pedant, it really helps if you don't fuck it up.

      OP said:

      > me and my friends together built an 8 bit CPU…

      – and if one replaces that with your suggestion:

      > My friends and I together built an 8 bit CPU…

      – you'll find that you are, gleefully, wrong.

      For those unaware, the simplest test for 'me and x' vs. 'x and I' is that, in the latter case, you should be able to remove 'x and', and have the sentence still make sense.

      For example, 'Me and Lucy went to the shops' is technically incorrect, because 'Lucy and I went to the shops' makes sense if we remove Lucy. 'I went to the shops'.

      The pendant's adjustment fails this test:

      > I together built an 8 bit CPU

  • momoraul 11 hours ago
    the rom-to-ram bootstrap is a nice touch. after it hands over, what stops the bootloader from writing to I-SRAM again? a mode flag in the control matrix?
  • dreamcompiler 9 hours ago
    "This makes the machine transparent in a way that microcode-based designs cannot be."

    Every output bit m of microcode can be equivalently expressed as a logic function of n inputs where the microcode has n incoming address lines. This no less transparent than pure logic if you know the contents of the microcode. Microcode is often preferred because changing it is much easier than changing a bunch of gate logic. IMHO factoring your design into registers vs. control signals and putting the control signals into microcode makes the design more transparent than having a giant sea of gates.

  • chrisakoury 4 hours ago
    Logisim was the shit back in Uni

    Very implressive tbh

    You should include a screenshot of the logisim diagram

  • bcjdjsndon 3 hours ago
    That ipc lol were all 8bit CPUs less than1 instruction per cycle?
  • hahooh 4 hours ago
    amazing 2nd year i was playing starcraft all day
  • HerbManic 11 hours ago
    With all the talk about developers being lazy and younger folk not understanding the technology they use, it is always great to see examples of core foundational work still being done. Makes the rest of that talk feel like fear mongering.
    • wl 8 hours ago
      I did an undergraduate electrical engineering degree some years ago. Building a CPU much like this one was the final project in our second digital design class. The difference here from the usual approach, as they point out, is that this is a gate-by-gate design you could assemble out of 74-series logic gates on a breadboard rather than the more common Verilog/VHDL designs that target FPGAs. Definitely a more tedious, time consuming approach, but I'm not convinced it's more conceptually difficult. By the time you're building a CPU, you've probably already built the component parts like the adders out of pure logic gates, anyway.

      Not to say that this is easy, but I think you'd find that a whole lot more people are doing this kind of thing than you might think.

  • andrewvu0203 7 hours ago
    [flagged]
  • rahadbhuiya 2 hours ago
    [dead]
  • roshiya 1 day ago
    [dead]
  • hypfer 8 hours ago
    Neat!

    Now do it the other way round and make the 8 bit cpus become a 2nd year EE student.